1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a chip layout of a semiconductor memory.
2. Description of the Related Art
The demands of nonvolatile semiconductor memories which can easily store sound and images and memory cards which contain the nonvolatile semiconductor memories are rapidly expanded with the spread of digital still cameras and camera-equipped mobile phones. In the above application, since a large capacity memory is required, it is important to suppress the bit-unit price of the memory so as not to apply a heavy burden to the user.
In order to keep the bit-unit price low and provide an inexpensive nonvolatile semiconductor memory with large capacity, it is effective to reduce the chip area and enhance the manufacturing yield. In order to achieve these, it is necessary to devise a good way so as to easily make the chip layout with a small area.
An example of the chip layout which is now well known in the art is described in U.S. Pat. Specification No. 5,625,590 (Reference Document 1) and Jpn. Pat. Appln. KOKAI Publication No. 2001-217383 (Reference Document 2), for example.
Reference Document 1 is an example in which row decoders are arranged on both ends of a memory cell array.
Reference Document 2 is an example in which pad strings are arranged on a line.